The field of the invention relates to bused digital intercommunication and interconnect, and more particularly to certain control features of digital buses wherein arbitration as a means for resolving priority for bus access is fully distributed amongst bus user devices.
It is known in the prior art that arbitration, under a priority basis, for bus access amongst a number of contending units attached to such bus can be distributed, or performed simultaneously by replicated arbitration circuits contained within each of the bus-interconnected devices. Distributed arbitration for resolving priority in bus access is taught in U.S. Pat. No. 4,320,457 for COMMUNICATION BUS ACQUISITION CIRCUIT to Tanikawa [hereinafter Tanikawa]. Distributed bus arbitration wherein such arbitration is also time-phased, or conducted upon the same physical bus lines during a plurality of communication cycles, is taught in U.S. patent application, Ser. No. 356,051 for VERSATILE INTERCONNECTION BUS to D. B. Bennett, et al. [hereinafter Bennett]. The prior art in general teaches that arbitration for bus access at the distributed arbitration circuits within each of the bus-interconnected devices is synchronized by the ocurrence of a communication signal upon the bus. It is also generally taught in the prior art that the arbitration circuits at each device contending for bus access may arbitrate amongst N+1 total said devices on N arbitration bus lines in order to resolve a single, highest priority, one of such devices which wins arbitration and gains ownership of the digital communication bus for a communication thereon, which communication may transpire over a multiplicity of cycles. The prior art teaches that the activities of arbitration and data transfer may be time-overlapped, or pipelined in their occurrence (upon separate dedicated communication lines) upon the digital communication bus. The teaching of Bennett shows that plural such cycles of arbitration may be, to such extent as is possible, time-overlapped, or pipelined, with plural cycles of data transfer.
The present invention is concerned with certain particular control, or protocol, procedures in the distributed conduct of arbitration on synchronous digital communication buses. This control, or protocol, exists both between the User digital logic devices and those bus interface logics (such as are the subject of the present disclosure) which the User will communicate through to and from the digital communication bus, and as particular control, or protocol, signals carried upon the digital communication bus. The conduct of those control procedures implemented by the method and apparatus of the present invention generally are utilized, and make sense, only within the context of distributed arbitration for a digital bus. Within such a context, the control procedures of the present invention accomplish certain useful effects in the conduct (or nonconduct) of distributed arbitration. However, the effects of these control procedures--which include the effective implementation of "snapshot" priority (to be explained) and the ability of a highest priority user to stop the bus--have analogues in those effects accomplishable at a single, centralized, arbitrating authority when arbitration for a digital bus is not distributed. Generally, to accomplish during distributed bus arbitration that which may be more simply performed when arbitration is centralized will require those new control procedures which are the subject of the method and apparatus teaching of the present disclosure.
A first specific aspect of the method and apparatus for the control of distributed arbitration upon a digital communication bus in the present invention will be seen to be that a bus control line is instituted, called a REQUEST INHIBIT signal line, whereby each bus-interconnected arbitrating device may be inhibited from the registration of further, new requests beyond those already pending in arbitration. It is taught in the prior art that the single highest priority, arbitration-winning, bus-owning one of the contending devices may actuate a control line, called a PRIORITY DISABLE signal line within the circuit of the present invention, to suspend other bus-arbitrating devices from gaining, responsively to such arbitration, control of the bus in order that the present bus-controlling device may maintain bus control for a plurality of communication transfers during a like plurality of communication cycles thereon such bus. The first specific aspect of the present invention is not equivalent to the disablement or suspension of arbitration as by the PRIORITY DISABLE signal line or counterpart signals within the prior art, but rather allows arbitration to continue between all bus-interconnected arbitrating devices which have already registered requests for bus access. The intent of such an implemented capability is that a low priority bus requestor should be able to obtain access to an arbitrated digital communication bus in the face of such number and frequencies of higher priority requests as would normally block out the recognition of such lower priority requesting device.
This manner of the present invention in granting priority, whereby low priority devices may obtain access to a heavily contested bus system, is conceptually akin to prior art methods of implementing "shapshot" priority between multiple requestors contending for access to a single, multi-ported functional unit such as a memory. In such a system all pending requests are frozen, akin to a photographic "shapshot", at a time certain. The multi-accessed device, such as a memory, will then sort through all pending requests in a priority order, eventually thusly ensuring the servicing of even the lowest priority pending request at the time of the "snapshot". Implementation of such a concept when the arbitration is not centralized within a single device, such as the hypothetical memory device, is one subject of the present invention.
Of particular pertinence to the first aspect of the present invention, the prior art method and apparatus of Tanikawa prevents the single, highest-priority requestor from obtaining consecutive accesses to a contested bus. As explained at specification column 4, line 59-68 of Tanikawa "the [arbitration] lines . . . are coded to indicate the priority number of the highest priority contending device. However, once the highest priority device gains access to the bus . . . the priority number of the associated device is in effect removed from the [arbitration] lines of the bus. The setting of these lines is then conrolled by the highest priority device of the remaining contending devices seeking access to the bus." Thus the circuit of Tanikawa assures alternate servicing of at least the two highest priority contending devices, regardless of their frequency of request. Applicants' invention will suffice to service low, and even lowest, priority requestors even when access to the single, system bus, resource is so heavily contested that, under the prior art scheme of Tanikawa, only some lesser number of higher priority requestors would constantly win arbitration and control the single system bus resource, locking out lower priority requestors.
Also of particular pertinence to the first aspect of the present invention, in an alternative prior art solution the basic concept that certain, lower, priority devices may experience conflict to the point of lockout in contending, via arbitration, for access to a system bus is dealt with in the teaching of Bennett at his section 1.4: Distributed, Time-Phased Selectable Priority Arbitration. Bennett teaches an apparatus in which "intelligent" User devices may change their arbitration priorities for access to a system bus in accordance with their perceived need, or urgency, and their success in arbitrating for such bus at each increasing priority level. Of course, such User assumed multiple arbitration priority codes must be correlated with an over all system design plan. Allowing arbitration between up to 256 arbitration code identifications (assumed unique ones at any time by each interconnected device), the apparatus of Bennett supports the ultimate scheme wherein each User may arbitrate for the bus at a graduated, current processing dictated, priority. The variable arbitration so conducted is not of the "shapshot" conceptual type, however, and does not represent the ability of each unique ones of the interconnected devices to inhibit the requests of other devices to arbitrate the bus (thereby ultimately assuring its own access) as in the present disclosure, but rather to dynamically alter (within system-level constraints) its own priority of arbitration, leaving all other arbitrating devices unaffected.
As a second aspect of the present invention, User logics, being those logic circuits which utilize the bus through the arbitration logics, will be able to (in a timely manner) cancel a request previously made to arbitrate the bus. A similar concept of the cancellation of pending activities upon a digital communication bus is dealt with in the prior art reference of Bennett at his specification section 6.5: Versatile Bus Interface Logics to User Interface for the Special Operation of Cancelling a Pending Transaction, and accompanying FIG. 52e. The cancellation with which Bennett is concerned is, however, not that of distributed arbitration but rather of subsequent words in a multi-word data message, such multi-word messages as are generally permitted upon the digital communication bus of Bennett. As will be seen from the subject of the present disclosure, when User logics register a request to the arbitration circuitry for the conduct of arbitration upon a digital communication bus upon its behalf, then such request normally suffices to set an arbitration request flip-flop. Such a flip-flop is normally cleared upon the successful arbitration for the bus. Applicants teach a method and an apparatus by which a User may cancel its own pending request, thereby removing itself from arbitration, even should (and only if) such arbitration not have culminated in the winning of the bus by such particular User device.
As another point of comparison between the second aspect of the present invention, wherein each bus-interconnected device may cancel its own pending arbitration request, to the prior art disclosure of Bennett, it should be noted that the User logics interface to the synchronously timed versatile bus interface logics of Bennett do not require that an arbitration be completed successfully for such User. Rather, as shown in FIG. 88d of Bennett, the User logics will synchronously (in a timed relationship) indicate its intent to arbitrate within each present bus arbitration cycle via raising the High condition of equal (H) INIT TRANS meaning initiate transaction. During the High persistence of signal (H) AUTO RETRY, meaning retry arbitration, one only occurrence of this initiate transaction signal will suffice to cause the interface logics to continue arbitrating in the User's behalf, until and unless, the User wins ownership of the bus. If, however, the User does not create the logical true condition of signal (H) AUTO RETRY, then the User will arbitrate, successfully or unsuccessfully, once only for the ownership of each bus upon each occurrence of logically high signal (H) INIT TRANS. Thus the synchronous system of Bennett, as regards the capability of a user to synchronously discontinue arbitration requests, is essentially different than the apparatus and method of applicants wherein an arbitration request previously registered may be deregistered, or cancelled.
As a third aspect of the present invention, a method and apparatus will be taught whereby the User device arbitrating at the single highest bus priority may, through interface logics which are identically replicated in the interfacing of the bus to all Users, cause all bus activity save the arbitration to stop. The method and the apparatus of the present invention will teach that the single, highest priority, User requestor which is stopping the bus will cause to be maintained active a highest priority bus request line, thereby locking out other lower priority units. Meanwhile such highest priority User requestor is suspended from recognition that it has won arbitration for the bus. In such a state arbitration is perpetually conducted upon the bus, but the highest priority, arbitration-winning user does not recognize that it has won arbitration. In such a state, the system clock which controls the timing of the bus may be switched between alternative sources, including alternative sources variant in frequency, while the bus is suspended, or stopped, from conducting data transfer activity. The prior art teaches buses that are stoppable, or which can be stopped by individual requestors, but by methods and apparatus which are alternative to those of the present invention. A communication cycle on the prior art bus of Bennett is enabled only by the generation of a NOT BUSY signal by the bus-owning current master one of the interconnected devices. Arbitration on the prior art bus of Tanikawa similarly uses a busy-type signal, called BUSY, which is driven by the bus-owning master one device, in enablement of the conduct of arbitration. The busy-signal of Iawikawa cannot prevent the next single from transpiring, but the maintenance of such signal in the false condition can assure that bus activity (at least such activity as is not performed by the bus-owning master one device) will cease. Thusly, in the prior art circuits any current bus-owning master device could stop the bus. In the circuit and method of the present invention only the highest priority device, regardless of whether such device is a priori knowledgeable of its higher priority condition, will be successfully able to stop the bus. Additionally, the clock source may be switched, including in frequency, for the bus of the present invention during the stopped condition. This concept has not been explicitly dealt with in the prior art although the versatile bus of Bennett could, as a bus synchronously timed with the User devices, suffice to sustain an orderly stop should the clock in use be suspended with both phases in the logical Low condition, and a new clock (potentially at a different frequency) instituted to resume timing at the phase previously left off from.